This invention relates to an oversampling analog-to-digital (A/D or A-to-D) converter for sampling an input analog signal at an oversampling frequency and producing an output digital signal.
An oversampling A/D converter is ordinarily manufactured by using a very large scale integration technology. Such converters have significant promise in digital communication applications. In an oversampling A/D converter, an input analog signal of an input signal frequency bandwidth is sampled and each sample is converted into an output digital signal at an oversampling frequency. The oversampling frequency is much higher than the input signal frequency bandwidth, for example, higher than one hundred times the input signal frequency bandwidth.
An example of the oversampling A/D converter is discussed in a paper contributed jointly by Akira Yukawa, Rikio Maruta, and Kenji Nakayama to Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing held in March 1985, pp. 1400 to 1403, under the title of "An Oversampling A-to-D Converter Structure for VLSI Digital CODEC's".
The oversampling A/D converter according to Yukawa et al, employs a large integrating capacitor. Accordingly, the time constant attributable to the output resistance of its operational amplifier and this integrating capacitor is correspondingly large. As a result, a long static time of the integrating capacitor is required every time the polarity of the input analog signal is inverted. High speed operation is thereby prevented.
This problem may be solved with a balanced A/D converter in which two electric charge redistributing D/A converters are connected in parallel as described by Yukawa in European Patent Application (EP application) publication number A2 0169535. Specifically, the static time of the integrating capacitor is shortened by inverting the connections between the D/A converters and input terminals when the polarity of the input analog signal changes. An oversampling A/D converter according to the EP application, however, uses a balanced operational amplifier as integrator, so that the circuit dimensions are increased and a greater consumption of power is inevitable. Moreover, the increase in operating speed is limited to that than corresponding to the reduction of the static time.